(a) Fields of the Invention
The present invention relates to the structure of a stacked semiconductor module three-dimensionally constructed by stacking a second semiconductor device above a first semiconductor device. In particular, the present invention relates to the mount structure of the module.
(b) Description of Related Art
With a demand for size reduction and functionality enhancement of electronic equipment of various types including a cellular phone and a digital camera, attention is being given to a stacked semiconductor module which is made by stacking semiconductor devices each of which has electronic components, particularly, one or more semiconductor chips mounted to a semiconductor substrate.
In the stacked semiconductor module, stacking of semiconductor devices can significantly reduce the footprint thereof on a circuit substrate. Furthermore, the module employs only semiconductor chips which have been subjected, before mounting to a semiconductor substrate, to inspections up to and including a burn-in test and then recognized as conforming chips, so that the reliability as a module can be insured more certainly.
The method in which semiconductor chips are mounted to a semiconductor substrate formed with interconnects, however, tends to cause bowing of the semiconductor substrate in mounting the semiconductor chips to the semiconductor substrate, which degrades the reliability of connection between the stacked semiconductor devices. In addition, for this method, it is difficult to mount chips of different types.
To solve such a problem, a module structure as a first conventional example (see, for example, Japanese Unexamined Patent Publication No. 2004-281919) is shown which includes: a first semiconductor substrate; a first semiconductor chip mounted to the first semiconductor substrate; a second semiconductor substrate; a second semiconductor chip mounted to the second semiconductor substrate; protruding electrodes for connecting the first and second semiconductor substrates so that the second semiconductor substrate is held just above the first semiconductor chip; and a sealing material for sealing the second semiconductor chip so that the arrangement area of the protruding electrodes is also contained in the sealed region.
With this structure, the sealing material with the second semiconductor chip sealed therein can reinforce the arrangement area of the protruding electrodes in the second semiconductor substrate and suppress an increase in the height of the stacked semiconductor module in mounting the second semiconductor substrate to the first semiconductor substrate. Moreover, bowing of the second semiconductor substrate to which the second semiconductor chip is mounted can be reduced. Therefore, the semiconductor module made by stacking the semiconductor devices in the manner described above can prevent degradation of the reliability of connection between the first and second semiconductor substrates, and concurrently save the mounting space of the semiconductor chips.
As a second conventional example, a stacked module structure (see, for example, Japanese Unexamined Patent Publication No. 2004-281633) is shown which is made by staking a plurality of semiconductor chips. In each of the semiconductor chips in this structure, the top surface thereof perpendicular to the stacking direction is provided with a mounting terminal for use in mounting and an inspection terminal for inspecting the quality thereof, and the bottom surface thereof perpendicular to the stacking direction is provided with a mounting pad connected to a mounting terminal of adjacent semiconductor chip and an inspection pad electrically continuous with its own inspection terminal.
In the stacked module thus constructed, to an inspection pad of a semiconductor chip having been already mounted, an inspection terminal of another semiconductor chip to be stacked is joined to receive an inspection signal from the joined inspection terminal electrically continuous with the inspection pad of the mounted semiconductor chip, thereby carrying out an inspection. If the result of the inspection is acceptable, the inspected semiconductor chip to be stacked is moved onto the plane flush with the mounted semiconductor chip, that is, moved on the plane perpendicular to the stacking direction and in parallel with the substrate. Then, the mounting terminal of the semiconductor chip to be mounted is connected to the mounting pad of the mounted semiconductor chip to stack these chips.
With this procedure, the quality inspection of the individual semiconductor chips to be stacked can be carried out easily before stacking of the respective chips. Moreover, since the semiconductor chips to be stacked do not have to be mounted to the semiconductor substrate, the total dimension of the module can be decreased. Furthermore, since a series of steps for mounting the semiconductor chips to the semiconductor substrate are eliminated, time and labor necessary for fabrication of the module can be reduced and yield of the stacked module can be improved.
In the first conventional example, the protruding electrodes (solder ball bumps) for connecting the second and first semiconductor devices are connected in a region of the back side of the second semiconductor substrate lying outside the semiconductor chip mounting region, that is, in a region corresponding to the arrangement region of the sealing material. From this structure, if the semiconductor chip is large in dimension or a plurality of semiconductor chips are mounted, the shape of the second semiconductor substrate, eventually, the shape of the first semiconductor substrate is also large. This results in arrangement of the solder ball bumps on a wide area. Consequently, faulty connection portions are created easily in applying an impact from outside, thermal stress, or the like. As a result, the semiconductor devices in the first conventional example are likely to offer a degraded reliability.
In the second conventional example, the module has the structure in which the semiconductor chips are stacked directly on the semiconductor substrate and further the respective semiconductor chips are needed to be provided with vias. From this structure, when comparison is made with a conventional semiconductor chip, the chip in this example has a greater chip area. Moreover, this example requires an etching process for forming a via in the semiconductor chip, which makes the fabrication process of the semiconductor chip complicated. These problems lead to an increased cost of the semiconductor chip. In addition, it is relatively difficult to conduct a burn-in test on the semiconductor chip before stacking to sufficiently check the reliability thereof.